1. Target device : Cyclone V SoC
2. External Memory : DDR3 1Gb
The design leverages the ability for users to send Avalon® Memory Mapped commands over JTAG. The Avalon-MM commands are routed to a JTAG to Avalon Master Bridge, which is tied to the FPGA To HPS AXI™ Bridge on the HPS. From there the data is directed into the L3 Interconnect where it is routed based on the destination address. A command with the appropriate destination address is routed to the SDRAM Controller Subsystem where it will ultimately be executed.
Figure 1. Design Example Block diagram
The 1GB of memory is partitioned using two rules. The first rule sets the access region for the MPU. The MPU is granted access from 0MB to 512MB. The second rule sets the access region for the L3 Interconnect. The L3 Interconnect has access from 319MB to 1,024MB. The overlap of these two rules results in a "Shared" region which both the MPU and L3 interconnect can access.