Standard AXI-stream bus

댓글 0

[통신]

2021. 5. 10.

 

Standard AXI-stream bus

AXI4-StreamThe address item is removed, allowing unlimited data burst transmission scale.

1. Interface signal description

signal

source

description

ACLK

Clock source

Global clock signal. All signals are sampled on the rising edge of the ACLK signal.

ARESETn

Reset source

Global reset signal. ARESETn is active low.

TVALID

the Lord

TVALID indicates that the master device is driving a valid transmission. When both TVALID and TREADY are set, a transfer occurs.

TREADY

From

TREADY indicates that the slave device can receive a transmission in the current cycle.

TDATA[(8n-1):0]

the Lord

TDATA is the basic payload used to provide data across the interface. The data is an integer number of bytes.

TSTRB[(n-1):0]

the Lord

TSTRB byte modifier. Used to describe the contents of TDATA related bytes as a data byte or a location byte is processed.

TKEEP[(n-1):0]

the Lord

TKEEP is a byte modifier. Used to indicate whether the contents of TDATA related bytes are processed as part of the data stream. Those related bytes whose TKEEP byte modifier is not confirmed are null bytes and can be removed from the data stream.

TLAST

the Lord

TLAST indicates the boundary of the packet.

TID[(i-1):0]

the Lord

TID is the identifier of the data stream, used to indicate different data streams.

TDEST[(d-1):0]

the Lord

TDEST provides routing information for data streams.

TUSER[(n-1):0]

the Lord

TUSER is user-defined sideband information, which can be sent with the data stream.

Second, the handshake mechanism

Only when both VALID and READY are high at the same time can the transmission be performed.

VALIDThe sequence of the READY signal has the following three forms:

 

2.1 VALIDEarlier than READY signal

 

2.2 READYThe signal is earlier than the VALID signal

 

2.3 VALID The signal is the same as the READY signal

Standard AXI4-stream timing

The difference between AXI4-Stream and AXI4 is that AXI4-Stream removes the address line, so that it does not involve the concept of reading and writing data, only a simple send and receive statement, reducing latency. Since the AXI4-Stream protocol (amba4_axi4_stream_v1_0_protocol_spec.pdf) does not have a timing diagram, I use a timing diagram in the product instruction manual of XILINX (pg007_srio_gen2.pdf) to demonstrate the relationship between the signals of AXI4-Stream. As shown below:

 

In the above figure, the ready signal is always at a high level, indicating that the slave device is ready to receive data. When tvalid goes high, tdata, tkeep, and tuser also send at the same time. At the last byte of tdata, tlast sends a high-level pulse. After the data is sent, tvalid goes low. Such a transfer is completed.

 

Introduction to Aurora Interface

 

The user-side interface can be configured in framing/streaming mode,

The current 722 project is configured in framing mode,The interface is defined as follows:

USER_DATA_S_AXIS_RX

m_axi_rx_tdata[0:63]

output

64bit

The 64-bit frame data output from the aurora interface to the module, bit[0:63] is arranged from high to low from right to left.

m_axi_rx_tkeep[0:7]

output

8bit

The last byte of the frame data output by the aurora interface to the module is the number of valid bytes. bit[0:7] Each bit represents a valid byte, and the number of accumulated bits of 1 is the number of valid bytes.(streamingNot available in mode)

m_axi_rx_tlast

output

1bit

Aurora interface output to the module frame data frame end flag(streamingNot available in mode)

m_axi_rx_tvalid

output

1bit

Frame data valid flag output by the aurora interface to the module

USER_DATA_S_AXIS_TX

s_axi_tx_tdata[0:63]

input

64bit

The module outputs 64-bit frame data after the timing adjustment of the aurora interface ready, bit[0:63] is arranged from high to low from right to left.

s_axi_tx_tkeep[0:7]

input

8bit

The output of the module to the aurora interface's ready timing adjusted frame data is the last valid number of bytes, bit[0:7] each bit represents a valid byte, the number of accumulated bits is 1 is the number of valid bytes.(streamingNot available in mode)

s_axi_tx_tlast

input

1bit

Module output to the aurora interface ready timing adjusted frame data frame end flag(streamingNot available in mode)

s_axi_tx_tvalid

input

1bit

The module outputs the frame data valid flag after the timing adjustment of the aurora interface ready

s_axi_tx_tready

output

1bit

Aurora interface output ready flag

It can be seen that when the aurora interface mode is configured as streaming mode, it is very different from the standard AXI-stream interface.

FramingThe mode conforms to the AXI4-Stream protocol specification and contains the signals needed to send and receive frame data.

The data bit sequence is defined as follows:

 

Send timing diagram

The Aurora interface does not have a specific frame format (unlike the Ethernet phy interface). When s_axi_tx_tvalid and s_axi_tx_tready are both high, the data can be sent in the correct bit order. The following illustrates the transmission timing of the aurora interface.

Example1: Send 3 user_data

 

When s_axi_tx_tvalid and s_axi_tx_tready are both high, the data is valid.

When s_axi_tx_tvalid and s_axi_tx_tlast are both high, it indicates the last data.

s_axi_tx_tkeep valid byte flag, s_axi_tx_tkeep is valid at s_axi_tx_tlast.

 

Example2: Send intermittently, send 3 user_data

 

The user can suspend transmission by controlling s_axi_tx_tvalid during data transmission.

 

Example3: Data transmission with clock compensation

 

When s_axi_tx_tready is low, the user needs to suspend data transmission.

Receive timing diagram

Since there is no buffer in the receiving direction of aurora core, there is no ready signal,

 

When m_axi_rx_rvalid is high, the data is valid.

 

 

 

 

참조 : www.programmersought.com/article/38973897219/